The present invention concerns methods of making, or fabricating, integrated circuits, particularly methods of forming interconnects.
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then xe2x80x9cwired,xe2x80x9d or interconnected, together to define a specific electric circuit, such as a computer memory.
Interconnecting millions of microscopic components typically entails covering the components with an insulative layer, etching small holes in the insulative layer to expose portions of the components underneath, and then actually connecting the components through metallization. Metallization is the process of depositing a metal, usually an aluminum alloy, into the small holes and onto the insulative layer to form line-like, metallic paths, or wires, between the components. Photolithography, an optical-patterning technique, defines the particular wiring or interconnection pattern.
Frequently, several levels of metallization, sometimes as many as six or seven, are necessary to make a particular circuit. Such cases require covering each metallization level with insulation, etching holes to expose portions of an underlying metallization, and then depositing more metal to form additional wires, connecting the exposed portions of the underlying metallization.
Current interconnection techniques suffer from two significant shortcomings. First, because of limitations in the photolithography used to define metallization patterns, current techniques require digging trenches to ensure that deposited metallic lines are flush, or coplanar, with the surface of the underlying insulation. However, digging these trenches is a time-consuming step which ultimately increases the cost of manufacturing integrated circuits.
Secondly, current techniques yield interconnective structures of insulation and metal that are highly capacitive. High capacitance wastes power and slows the response of integrated circuits to electrical signals. Thus, current interconnection techniques stand in the way of faster and more-efficient integrated circuits.
Accordingly, there is not only a need for new interconnection methods that eliminate the trench-digging step, but also a need for new methods and interconnective structures that yield faster and more-efficient integrated circuits.
To address these and other needs, the present invention provides a new method of making coplanar metallic and insulative members for an integrated circuit. Specifically, one embodiment of the method entails forming a first layer that includes silicon and germanium, and then oxidizing a region of the first layer to define an oxidized region and a non-oxidized region. After oxidation, the method reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum alloy to form a metallic member flush or coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulative member having a low dielectric constant.
Thus, the method of the present invention yields a self-planarizing metallic structure that not only eliminates the time-consuming, trench-digging step of conventional methods, but also places the metallic structure within a low-dielectric insulation that allows faster, more-efficient integrated circuits.